Check out my website for up-to-date info: abapages.com

• Languages: SystemVerilog (RTL, DV, SVA), Python, C/C++, OpenCL, Bash, Tcl
• EDA Tools: AMD/Xilinx Vivado, Cadence Genus, Cadence Innovus, Synopsys Design Compiler
• Verification: Verilator, VCS, Xsim, Questa Formal, SymbiYosys, cocotb
• Other: Git, Docker, LaTeX, GitHub Actions

• SystemVerilog Course for 300 students: 64-hour short course, collaborating with Synopsys, covering RTL design, randomized transactional testbenches, AXI protocol design, FPGA & ASIC flow labs.

• CGRA4ML: An open-source, automated framework for scientific edge computing. Maps DNNs from Python to custom, parameterizable SystemVerilog CGRAs with C firmware, targeting FPGAs and custom ASICs. ACM TRETS paper

• AXI Stream Systolic Array & FireBridge:

  • A lightweight, highly parameterizable systolic array in SV, integrated with Ibex-SoC via AXI DMAs, a custom DMA controller, and corresponding C firmware. Currently being formally verified.
  • A framework for system-level verification enabling rapid Firmware/Hardware co-development. Bridges SystemVerilog AXI subsystems to real C firmware via DPI-C, without simulating a CPU.
  • Used as a testbed with scripts to implement an AXI IP on FPGAs, integrate with Ibex RISC-V CPU, etc.

• Formal AXI: A reusable Formal VIP for AXI4 and AXI5 protocols and for complex IPs like interconnects being built and tested against both open-source and commercial tools.

• AXI-Stream VIP: Reusable transaction-level AXI Stream Driver and Sink with parametrized, random stalls to stress-test the designs.

• UVM in 580-lines: Simplest possible complete UVM testbench, built as a class project.