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Starred repositories

4 results for source starred repositories written in Verilog
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UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

Verilog 144 22 Updated Jun 23, 2024

同济大学数字逻辑课程期末大作业

Verilog 55 4 Updated Sep 5, 2021

同济大学22级数字逻辑大作业

Verilog 32 Updated Oct 21, 2024

中国海洋大学计算机专业课程资料

Verilog 27 Updated Jun 11, 2025