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@0xhustlerr
hustler 0xhustlerr
Sr Full Stack | Blockchain | AI Engineer

@web @blockchain @AI Earth

@Greeshma-Siri
Narra Greeshma Siri Greeshma-Siri
ECE 2025 | VLSI Design Verification trainee | Verilog | SystemVerilog | TCL | UVM
@Yarok14Technologies
Yarok14 Technologies Yarok14Technologies
Shaping Silicon, Powering Intelligence. This prototype phase company is founded and owned by Bibin Nandhyattu Biji.

Yarok14 Kottayam, Kerala, India

@chumy6
Maren Chu chumy6
Hardware Accelerator & AI Chip
@trista-csee
Hua-Chen (Matilda) Wu trista-csee
Dynamic Verification Engineer proficient in FPGA co-design, UVM verification, and award-winning privacy solutions.

National Yang Ming Chiao Tung University Taiwan

@dirkarnez
Dirk Arnez dirkarnez
Freelance Software Engineer | Composer | Mixer | Multi-instrumentalist

Freelance Hong Kong

@OfficialCodeVoyage
Pavlo Bondarenko OfficialCodeVoyage
product | Claude Code very active user

Denver, CO

@chipnertkj
Piotr Wyszomirski chipnertkj
Software Developer, Musician

Poland

@sura-sivareddy
SURA SIVAREDDY sura-sivareddy
Masters in Electrical Engineering @ IIT Kanpur
@SudheerJanagama
Sudheer Anand SudheerJanagama
VLSI Frontend | Digital Design and Verification
@Prananya123
Prananya M Prananya123
I Intend to establish myself as a VLSI professional looking forward to a long term career in the field of VLSI, contributing to the com
@neilwang0913
YQ neilwang0913
Designer: "Work hard in silence, let success make the noise"

United Kingdom

@mitoksim
Timothy mitoksim
Engineering Profesional

California

@ishfaqahmed29
Ishfaq Ahmed ishfaqahmed29
⚡ Embedded Systems Engineer | Focusing on RTL Design & Verification | Bachelors in Electrical Engineering

Toronto, Canada

@shayan-taheri
Shayan (Sean) Taheri shayan-taheri
Software Engineer at HonestRank LLC. American Permanent Resident. Finance. Business. Management. Marketing.

Atlanta, Georgia, America

@vadakkodan
Pradeep Purushothaman Vadakkodathu vadakkodan
BE. Electronics and Communication | SoC/FPGA/ASIC/IP RTL Design Engineer | AMD/Altera/GOWIN FPGAs | Verilog/VHDL/SystemVerilog.

Freelancer Bengaluru

@Gaganabbot
Gagan Abbot Gaganabbot
Data Engineer | Consultant | Wipro | Ex Mindfire

Wipro Delhi, India

@bleauchat1995
bleauchat1995

HUST Wuhan Hubei

@lakshay1704
AnZerd.IB lakshay1704
Intellectual Badass

Might be New Delhi, India

@aleemrehaman
aleemrehaman

Intel Technologies Bangalore

@gitCyan
Max gitCyan
FPGA/ASIC/SOC

Beijing

@dalindev
Dalin Huang dalindev
“Stay Hungry, Stay Foolish”

Canada

@KevinHock
KevinHock
0.01x Engineer. The (Myspace) Tom of GitHub. 11% of pre-tax income to effective altruism charities.

SecEng @sierra-inc Formerly @grammarly, @pinterest, @Yelp I love San Francisco

@Senjai
Richard Wilson Senjai
My most productive days are measured by expletives per hour. I'm easy to spot, just look for the guy with speakers attached to his ears.

@opendoor-labs Montreal, QC, Canada

@veeYceeY
0x80FE veeYceeY

United Kingdom

@tonykevin
Tony kevin tonykevin
💻 Hi! Let's explore computer languages and nature. 🚀 🌊 🌋 🌵

Perú

@MichalPaszkiewicz
Michal J A Paszkiewicz MichalPaszkiewicz
Just a guy who likes to make things @MichalYouDoing

Scriptorium AI Gloucester, UK

@naviace
Navi naviace

Global India

@SathyaBhat
Sathyajith Bhat SathyaBhat
Author: Practical Docker with Python (@Apress) & co-author @cdkbook Organizer @BarcampBangalore @cdkday

Sydney, Australia

@d1g1t
Sandeep d1g1t

Mangalore, India