AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Caliptra IP and firmware for integrated Root of Trust block

OpenTitan: Open source silicon root of trust

VeeR EH1 core

Verilator open-source SystemVerilog simulator and lint system