Memory Acess Controller (MAC)
This module is to interface with sram, dealing with requests coming from MAI and changing the protocol to bank, row, col. 
*Jun.18.2014
 Construct the architecture of MAC
*Jun.19.2014
 Write the spec of MAC on the wiki of https://github.com/alexzhang007/Mac/wiki
 Write the verilog of MAC RTL.
*Jun.20.2014
 Write the RTL of Reorder Processor
*Jun.23.2014
 RTL compile is passed for Reorder Processor
*Jun.25.2014
 In order buffer is OK, start the logic for reorder buffer
*Jun.26.2014
 Change the IOB to the synchronize fifo.
 Change the ROB to the asynchronize fifo.
 Finish the single WrReq to Reorder processor
 Add an additional reorder_processor.v
*Jun.27.2014
 Add the command_generate module to interface with SDRAM
*Jun.28.2014
 Write request to sram is finished, but needs RTL compile pass
*Jul.01.2014
 Write request to sram is passed with one request. Supporting back to back write(no case has yet verified it). 
*Jul.02.2014
 Read request to sram is passed, but when integrating sdram model to TB, there is x in the input of sdram
*Jul.04.2014
 Write request can write data into sram, but read request can only read back one beat. Need support the burst mode 
*Jul.08.2014
 Write request has bug again for the changing the FSM logic sending out wrreq.  No daily RTL update.
*Jul.09.2014
 Rewrite the FSM of sending DDR request to SDRAM. Single write and read request is passed. But there is risk bug about the model.



[1] ORGFXSoC-master/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ssram.v
[2] MT48LC2M32B2-512K x 32 x 4banks, Micro.