Summary

Adds a minimal self-contained Verilog testbench for the axi_ram module.

Details

• Performs one AXI write followed by readback to verify data integrity.
• Runs standalone under Icarus Verilog (iverilog + vvp).
• Generates tb_axi_ram.vcd for GTKWave.
• Complements existing Python/MyHDL cocotb tests by providing a Verilog-only regression path.

Expected Output

iverilog -o tb_axi_ram.vvp tb/tb_axi_ram.v rtl/axi_ram.v && vvp tb_axi_ram.vvp

PASS: write succeed to addr 4, data DEADBEEF