open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Risc-V journey thru containers and new projects

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Verilator open-source SystemVerilog simulator and lint system

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Main VirtualGL repository

Application for Mind Mapping, Knowledge Management, Project Management. Develop, organize and communicate your ideas and knowledge in the most effective way.

An unofficial assembly reference for RISC-V.

A Visual Guide to Pull Requests

Unsorted stuff

Emulator for rapid prototyping of Software Defined Networks

Pulse oximetry

Placeholder repo for RFCs wiki -- Add new proposals for ZF-Commons modules in the wiki.

Pretty RFC indexes and reformats RFC documents for easier discovery and viewing.

openFrameworks is a community-developed cross platform toolkit for creative coding in C++.

MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems

Verilog to Routing -- Open Source CAD Flow for FPGA Research

All open source file and project for OpenFPGAduino project

Simple way to handle fat files without committing them to git, supports synchronization using rsync

Graphical Java application for managing BibTeX and BibLaTeX (.bib) databases

Docear's desktop version (GPL)