Arquitetura de Software em Java

Sail RISC-V model

Biblioteca Livre Internacional 5

📚 Biblioteca de livros essenciais da área da programação. (Confira o meu novo projeto `SendScriptWhatsapp`)

Learn System Design concepts and prepare for interviews using free resources.

Data Structure Algorithms, (GenAI/ML) System Design, Machine Learning, DevOps coding interview practices

System Design and Design Pattern Books

Notes of the book System Desgin Interview - An Insider's Guide

Welcome to the SDE Interview Preparation Roadmap! This repository is not just about my personal journey; it's a collaborative space for collective learning. As I prepare for Software Development En…

PicoRV32 - A Size-Optimized RISC-V CPU

GNU toolchain for RISC-V, including GCC

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

RISC-V microcontroller IP core for embedded, FPGA and ASIC applications

The User Guide of XiangShan.

Verilog implementation of multi-stage 32-bit RISC-V processor

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

An open-source microcontroller system based on RISC-V

Open-source high-performance RISC-V processor

RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.

CORE-V Family of RISC-V Cores

An open-source 32-bit RISC-V soft-core processor