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Focusing
Argentine Computer Science student, and enthusiast.
I enjoy low-level development, emulators, compilers, among many other things.
Feel free to ask me anyth-
-
Renaiss
- Argentina
- in/allkern
Highlights
- Pro
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written in Verilog
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Verilog Ethernet components for FPGA implementation
RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel