Stars
Open-source, vendor-agnostic full-featured FPGA JTAG debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI
A minimal, open-source Image Signal Processor (ISP) for AMD FPGA, implemented in Verilog.
5G NR PHY SISO Simulation — SSB Synchronization, CFO/Noise Estimation
Uses GitHub Actions to build multiple container images and publishes them to registries.
pyTooling is a collection of arbitrary useful classes, decorators, meta-classes and exceptions.
Tiny version of RISC-V for low resource FPGA developed by ASIC lab, School of Electronics , KIIT University
RF Transceiver Model with M-QAM Modulation (up to 1024).
FPGA design toolkit with templates and standard modules
An intro to embedded systems for ML application developers
This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Python-like test style while potentially improving simulation p…
A self-contained online book containing a library of FPGA design modules and related coding/design guides.
Mastering Embedded Linux Development Fourth Edition, published by Packt
Mastering Embedded Linux Programming Third Edition, published by Packt
My repository for studying FPGA Acceleration of Neural networks
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
Lessons to learn about Software Defined Radios (SDR) through GNUradio
VHDL development of the CASPER FFT for use in the CASPER toolflow.
casper-astro / casperfpga
Forked from ska-sa/casperfpgaSoftware control for CASPER FPGAs
FPGA receive-only SDR: real-time spectrum analysis + configurable IIR filters over UART/Ethernet.
BRAM Mapping Discovery in FPGA Design with MATLAB HDL Coder
Package manager and build abstraction tool for FPGA/ASIC development
Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.
IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet