Skip to content

Conversation

@Villyam
Copy link
Contributor

@Villyam Villyam commented Jun 23, 2025

PR Description

  • Adding spi_engine_interconnect_ctrl interface to spi_engine IPs.
  • Adding new project script features:
    • Block design make parameter injection.
    • Top module make parameter injection.
    • Simulation project script option.
  • projects/common/lfcpnx: Updating base design and IP versions.
  • ad738x_fmc/lfcpnx: Adding suport for Lattice LFCPNX-EVN carrier.
  • docs/user_guide/build_hdl.rst: Updates for first project.
  • docs/projects/ad738x_fmc/index.rst: Updates for Lattice Lattice LFCPNX-EVN carrier support.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

ladace
ladace previously approved these changes Jun 30, 2025
Copy link
Contributor

@ladace ladace left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Approved, fix Iulia's change requests

@bia1708
Copy link
Collaborator

bia1708 commented Jul 10, 2025

RetriggerCI

@Villyam Villyam force-pushed the lattice_add_ad738x_fmc_lfcpnx branch from 9033efe to 6f02fd8 Compare July 10, 2025 15:06
@Villyam
Copy link
Contributor Author

Villyam commented Jul 10, 2025

  • Updated Copyrights.
  • Fixed documentation related request.

@Villyam Villyam requested review from IuliaCMoldovan and ladace July 10, 2025 15:11
@Villyam Villyam force-pushed the lattice_add_ad738x_fmc_lfcpnx branch 2 times, most recently from f05ff12 to d429ecc Compare December 2, 2025 14:08
@Villyam
Copy link
Contributor Author

Villyam commented Dec 2, 2025

Version 2

Added a fix for AXI STREAM input interface of the DMA. The wrapper generator generated TLAST=1 based on the Lattice AXI Stream interface definition for the AXI STREAM input of the DMA because we do not have that signal implemented on the SPI Engine Offload. This caused the DMA to stop the transaction after receiving the first offload data word. I forced the TLAST input of the DMA to 0 in block design to fix it.

Updated the base design and the design to match with the ZedBoard version (160 MHz SPI Engine clock).
Added make parameters.
Added clock constraints.

Added full design simulation support.

Extended the docs/projects/ad738x_fmc/index.rst.

@Villyam
Copy link
Contributor Author

Villyam commented Dec 5, 2025

Version 3.

  • Completed the requested updates.
  • Added the required Lattice Propel Builder IP install commands to the documentation and to the project readme file.

@Villyam Villyam requested a review from PopPaul2021 December 5, 2025 12:32
PopPaul2021
PopPaul2021 previously approved these changes Dec 12, 2025
Copy link
Contributor

@PopPaul2021 PopPaul2021 left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks good to me! I've built the design, and there are no major errors or critical warnings.

Copy link
Contributor

@StancaPop StancaPop left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Approved for the documentation related sections.

Copy link
Contributor

@IuliaCMoldovan IuliaCMoldovan left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Approved the doc changes

library/interfaces_ltt/interfaces_ltt.tcl: Updating SPI Master interface definition.
CI related updates for build path and clean.

Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
Adding parameter injection support for block design and top module:
	* projects/scripts/adi_project_lattice.tcl
	* projects/scripts/adi_project_lattice_pb.tcl

Updates for sysid_gen_sys_init_file compatibility in:
	* projects/scripts/adi_project_lattice_pb.tcl
	* projects/scripts/project-lattice.mk

Adding simulation project support.
The '<carrier>/sim.tcl' (default) simulation project file is sourced
(if exists) to create a simulation design in a similar way than the
project block designs are created. It is possible to create and
add simulation IPs and connect them to the block design wrapper module.

projects/scripts/project-lattice.mk: Adding FORCE to lib deps build.

Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
Adding sysid support.
Adding external UART for interrupt compatibility.
Updating IP versions.

Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
…rrier support.

Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
Adding default interface folder searching to Propel Builder
project build. The default interface folder name to search
in hdl/library is the 'interfaces_ltt'.

Updating the default relative build path for Lattice interface
build to 'ltt'. This is a CI related requirement.

Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
@Villyam Villyam force-pushed the lattice_add_ad738x_fmc_lfcpnx branch from c7aec8b to b89a1cc Compare December 16, 2025 15:18
@Villyam Villyam merged commit 6fb2044 into main Dec 16, 2025
7 checks passed
@Villyam Villyam deleted the lattice_add_ad738x_fmc_lfcpnx branch December 16, 2025 15:21
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Projects

None yet

Development

Successfully merging this pull request may close these issues.

7 participants