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Custom email/password authentication plugin for MedusaJS which can be used serverless, with custom http based cookie sessions with machine id scans
UpdatedOct 28, 2025 -
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neural-network-visualizer Public
Forked from cpldcpu/neural-network-visualizerNeural Network Visualizer for RISC-V Edge AI Workshop using VSDSquadron Pro
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news_rag_advanced Public
Forked from johnsmithm/news_rag_advancedJupyter Notebook UpdatedApr 16, 2025 -
semiconductor_packaging Public
Semiconductor Packaging and simulations using Ansys tools
MIT License UpdatedApr 6, 2025 -
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IHP-Open-PDK Public
Forked from efabless/IHP-Open-PDK130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
HTML Apache License 2.0 UpdatedFeb 28, 2025 -
sky130_ef_ip__simple_por Public
Forked from efabless/sky130_ef_ip__simple_porSimple PoR based on an RC filter
Shell Apache License 2.0 UpdatedFeb 26, 2025 -
sky130_ef_ip__adc3v_12bit Public
Forked from efabless/sky130_ef_ip__adc3v_12bit12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.
Verilog Apache License 2.0 UpdatedFeb 26, 2025 -
sky130_ef_ip__rdac3v_8bit Public
Forked from efabless/sky130_ef_ip__rdac3v_8bit8-bit resistor ladder DAC with 3.3V output range
MATLAB Apache License 2.0 UpdatedFeb 26, 2025 -
openlane-metrics Public
Forked from efabless/openlane-metricsRepository to store metric results for OpenLane 2.0.0+
UpdatedFeb 26, 2025 -
caravel Public
Forked from efabless/caravelCaravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
Verilog Apache License 2.0 UpdatedFeb 26, 2025 -
openlane2 Public
Forked from chipfoundry/openlane2The next generation of OpenLane, rewritten from scratch with a modular architecture
Python Apache License 2.0 UpdatedFeb 26, 2025 -
openlane2-step-unit-tests Public
Forked from efabless/openlane2-step-unit-testsStep-specific Unit Tests for OpenLane 2.0.0+
Verilog Apache License 2.0 UpdatedFeb 26, 2025 -
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EF_PSRAM_CTRL Public
Forked from efabless/EF_PSRAM_CTRLVerilog Apache License 2.0 UpdatedFeb 26, 2025 -
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frigate_analog Public
Forked from efabless/frigate_analogThe analog signal processing and timing frontend subsystems for the Frigate harness chip
Verilog Apache License 2.0 UpdatedFeb 26, 2025 -
chipignite_discover Public
Forked from efabless/chipignite_discoverHTML Apache License 2.0 UpdatedFeb 26, 2025 -
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mpw_precheck Public
Forked from efabless/mpw_precheckPython Apache License 2.0 UpdatedFeb 25, 2025 -
caravel_user_project Public template
Forked from efabless/caravel_user_projecthttps://caravel-user-project.readthedocs.io
Verilog Apache License 2.0 UpdatedFeb 25, 2025 -
sky130_ef_ip__samplehold Public
Forked from efabless/sky130_ef_ip__sampleholdAnalog 3.3V sample and hold circuit, with buffered output
Tcl Apache License 2.0 UpdatedFeb 25, 2025 -
ipm Public
Forked from efabless/ipmOpen-source IPs Package Manager (IPM)
Python Apache License 2.0 UpdatedFeb 24, 2025 -
nix-eda Public
Forked from chipfoundry/nix-edaNix derivations for EDA tools
Nix Apache License 2.0 UpdatedFeb 24, 2025
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