Starred repositories
OpenROAD's unified application implementing an RTL-to-GDS Flow
Verilator open-source SystemVerilog simulator and lint system
Chisel: A Modern Hardware Design Language
Examples and guides for using the OpenAI API
Google Research
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OpenProject is the leading open source project management software.
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
Infrastructure to enable deployment of ML models to low-power resource-constrained embedded targets (including microcontrollers and digital signal processors).
OpenTitan: Open source silicon root of trust
A dependency management tool for hardware projects.
Small footprint and configurable DRAM core
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
iic-jku / IIC-OSIC-TOOLS
Forked from efabless/foss-asic-toolsIIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
Common SystemVerilog components
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Official electron build of draw.io
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are disabled. Please only use release tarballs from the QEMU website.
A Fast, Low-Overhead On-chip Network
Dolphin is a GameCube / Wii emulator, allowing you to play games for these two platforms on PC with improvements.
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.