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Chisel: A Modern Hardware Design Language
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Random instruction generator for RISC-V processor verification
Open deep learning compiler stack for Kendryte AI accelerators ✨
An open-source microcontroller system based on RISC-V
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
The multi-core cluster of a PULP system.
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
An ATE Pattern Generator for PULP chips and JTAG Taps in general
RISC-V Core Local Interrupt Controller (CLINT)
Sphinx theme from Read the Docs
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
A tool to deploy Deep Neural Networks on PULP-based SoC's
Small footprint and configurable embedded FPGA logic analyzer
Small footprint and configurable Inter-Chip communication cores
Small footprint and configurable SDCard core
Small footprint and configurable JESD204B core
Small footprint and configurable PCIe core
Small footprint and configurable SATA core
Small footprint and configurable DRAM core