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TuShare is a utility for crawling historical data of China stocks

Python 15,144 4,438 Updated Mar 13, 2024

Deep dive into Claude Code internals — architecture, agent loop, context engineering, and more. / 深入解析 Claude Code 源码:架构、Agent 循环、上下文工程、工具系统等

2,652 616 Updated May 5, 2026

Run Claude Code v2.1.88 from leaked source - one command setup

TypeScript 194 260 Updated Mar 31, 2026

Rocket Chip Generator

Scala 3,795 1,271 Updated Jun 2, 2026

A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.

C++ 121 8 Updated Oct 31, 2024

A LaTeX beamer theme template for CQU students.

TeX 17 4 Updated Oct 25, 2022

Comprehensive tools and frameworks for developing foundation models tailored to recommendation systems.

1,039 672 Updated Sep 16, 2025

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。

Verilog 317 53 Updated Aug 16, 2018

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。

Verilog 1 Updated Aug 16, 2018

重庆大学博士学位论文LaTex模版,支持2023年格式要求

TeX 77 13 Updated Mar 30, 2024

An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据,输出标准的GZIP格式,即常见的 .gz / .tar.gz 文件的格式。

Verilog 156 35 Updated Sep 15, 2023

数字IC相关资料

1,482 361 Updated Jul 1, 2025

A highly optimized LLM inference acceleration engine for Llama and its variants.

C++ 905 102 Updated Mar 18, 2026

Github Pages template based upon HTML and Markdown for personal, portfolio-based websites.

SCSS 17,151 7,355 Updated May 28, 2026

Implementation of Denoising Diffusion Probabilistic Model in Pytorch

Python 10,607 1,284 Updated Feb 11, 2026

A “Toy” Script transoforms MLIR Affine Dialect to Dot Visualized Format

Shell 5 1 Updated Nov 21, 2023

Ali-loner的个人主页

TeX 131 35 Updated May 18, 2021

基于FPGA的FFT算法并行优化

C 13 Updated Mar 7, 2024

This Repo describle the hardware description of MDC in Chiesl hardware language

Verilog 7 Updated Sep 17, 2024

🌊 Digital timing diagram rendering engine

JavaScript 3,428 408 Updated Jun 13, 2026

Real-to-complex and complex-to-real FFT for Rust

Rust 102 14 Updated Mar 12, 2026

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

Verilog 62 9 Updated May 24, 2026

分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。

809 80 Updated Apr 21, 2023

帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目

5,498 796 Updated May 15, 2022

Fourier ACelerator Compiler Framework. Efforts have been taken to blind code for submission.

C 7 Updated Mar 14, 2022
Python 328 300 Updated Jun 9, 2026

DO NOT CHECK OUT THESE FILES FROM GITHUB UNLESS YOU KNOW WHAT YOU ARE DOING. (See below.)

C 3,079 709 Updated Jun 10, 2026

DRA+RISC-V Exploration Framework

C++ 21 8 Updated Jan 8, 2024

MLIR project for FDRA (Rocket CPU + TRAM CGRA)

9 Updated Aug 18, 2025
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