Winch: Implement avgr instructions for x64 with AVX #10228
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winch/codegen/src/isa/x64/masm.rs
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| match size { | ||
| OperandSize::S8 | OperandSize::S16 => self.asm.xmm_vpavg_rrr(lhs, rhs, dst, size), | ||
| _ => unimplemented!(), | ||
| } | ||
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Could we avoid this match here entirely and instead delegate the operand size invariant checks to the assembler?
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It's currently duplicated in both places, and I'm not sure if such duplication is worth it.
saulecabrera
approved these changes
Feb 14, 2025
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Part of #8093. Implements the following instructions:
i8x16.avgr_ui16x8.avgr_u