Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RTL, Cmodel, and testbench for NVDLA

A tiny Open POWER ISA softcore written in VHDL 2008

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

LicheeTang 蜂鸟E203 Core

A MIPS CPU implemented in Verilog

The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation…