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feat(tricore): Initial tricore support Arm Build #713: Pull request #242 synchronize by miguelafsilva5
3m 7s feat/tricore
feat/tricore
3m 7s
feat(tricore): Initial tricore support Code Quality #685: Pull request #242 synchronize by miguelafsilva5
2m 50s feat/tricore
feat/tricore
2m 50s
feat(tricore): Initial tricore support RISC-V Build #715: Pull request #242 synchronize by miguelafsilva5
2m 46s feat/tricore
feat/tricore
2m 46s
feat(tricore): Initial tricore support Bao component base workflow #713: Pull request #242 synchronize by miguelafsilva5
2m 37s feat/tricore
feat/tricore
2m 37s
feat(tricore): Initial tricore support RISC-V Build #714: Pull request #242 synchronize by miguelafsilva5
2m 47s feat/tricore
feat/tricore
2m 47s
feat(tricore): Initial tricore support Code Quality #684: Pull request #242 synchronize by miguelafsilva5
2m 4s feat/tricore
feat/tricore
2m 4s
feat(tricore): Initial tricore support Bao component base workflow #712: Pull request #242 synchronize by miguelafsilva5
2m 24s feat/tricore
feat/tricore
2m 24s
feat(tricore): Initial tricore support Arm Build #712: Pull request #242 synchronize by miguelafsilva5
3m 18s feat/tricore
feat/tricore
3m 18s
fix(riscv): explicitly set hstatus.vsxl for rv64 Code Quality #683: Commit 4ee3265 pushed by danielRep
2m 1s main
main
2m 1s
fix(riscv): explicitly set hstatus.vsxl for rv64 Arm Build #711: Commit 4ee3265 pushed by danielRep
2m 36s main
main
2m 36s
fix(riscv): explicitly set hstatus.vsxl for rv64 RISC-V Build #713: Commit 4ee3265 pushed by danielRep
2m 42s main
main
2m 42s
fix(riscv): explicitly set hstatus.vsxl for rv64 Bao component base workflow #711: Commit 4ee3265 pushed by danielRep
2m 39s main
main
2m 39s
feat(tricore): Initial tricore support Code Quality #682: Pull request #242 synchronize by miguelafsilva5
2m 0s feat/tricore
feat/tricore
2m 0s
feat(tricore): Initial tricore support RISC-V Build #712: Pull request #242 synchronize by miguelafsilva5
2m 20s feat/tricore
feat/tricore
2m 20s
feat(tricore): Initial tricore support Arm Build #710: Pull request #242 synchronize by miguelafsilva5
2m 14s feat/tricore
feat/tricore
2m 14s
feat(tricore): Initial tricore support Bao component base workflow #710: Pull request #242 synchronize by miguelafsilva5
1m 58s feat/tricore
feat/tricore
1m 58s
feat(tricore): Initial tricore support Arm Build #709: Pull request #242 synchronize by miguelafsilva5
2m 3s feat/tricore
feat/tricore
2m 3s
feat(tricore): Initial tricore support Bao component base workflow #709: Pull request #242 synchronize by miguelafsilva5
1m 55s feat/tricore
feat/tricore
1m 55s
feat(tricore): Initial tricore support RISC-V Build #711: Pull request #242 synchronize by miguelafsilva5
1m 59s feat/tricore
feat/tricore
1m 59s
feat(tricore): Initial tricore support Code Quality #681: Pull request #242 synchronize by miguelafsilva5
1m 47s feat/tricore
feat/tricore
1m 47s
feat(tricore): Initial tricore support RISC-V Build #710: Pull request #242 synchronize by miguelafsilva5
2m 16s feat/tricore
feat/tricore
2m 16s
feat(tricore): Initial tricore support Bao component base workflow #708: Pull request #242 synchronize by miguelafsilva5
1m 57s feat/tricore
feat/tricore
1m 57s
feat(tricore): Initial tricore support Code Quality #680: Pull request #242 synchronize by miguelafsilva5
1m 47s feat/tricore
feat/tricore
1m 47s
feat(tricore): Initial tricore support Arm Build #708: Pull request #242 synchronize by miguelafsilva5
2m 9s feat/tricore
feat/tricore
2m 9s
Modify riscv RV32/RV64 macro logic and set hstatus vsxl for rv64 Bao component base workflow #707: Pull request #291 synchronize by josecm
1m 53s fix/riscv_set_hstatus_vsxl
fix/riscv_set_hstatus_vsxl
1m 53s