Verilog Ethernet components for FPGA implementation

CAN-bus Controller with AXI4-lite Interface

AXI interface modules for Cocotb

An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!

🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

A simple RISC-V processor for use in FPGA designs.

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

Verilog library for ASIC and FPGA designers

Wireless JTAG 'cable' for Xilinx FPGAs. This is an 'English fork' of https://github.com/ciniml/xvc-esp32 project.

Verilog PCI express components

Open source FPGA-based NIC and platform for in-network compute

The RIFFA development repository

AMD OpenNIC Shell includes the HDL source files

Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

IP Cores that can be used within Vivado

Coroutine Co-simulation Test Bench

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe

Python interface to PCIE

MicroPython port package for RT-Thread

OpenTitan: Open source silicon root of trust

An IoT Solution,this is the android release app | download ios app in app store

A platform for building proxies to bypass network restrictions.

Must-have verilog systemverilog modules