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This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction scheduling.
Docker image and scripts to run EDA (including Synopsys/Cadence/Siemens/...) tools in a containerized environment.
A next.js web application that integrates AI capabilities with draw.io diagrams. This app allows you to create, modify, and enhance diagrams through natural language commands and AI-assisted visual…
A machine learning accelerator core designed for energy-efficient AI at the edge.
Maple Mono: Open source monospace font with round corner, ligatures and Nerd-Font icons for IDE and terminal, fine-grained customization options. 带连字和控制台图标的圆角等宽字体，中英文宽度完美2:1，细粒度的自定义选项
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
A neovim plugin to run lines/blocs of code (independently of the rest of the file), supporting multiples languages
A plugin for instantiate module automatically in neovim.
Smooth scrolling for Vim done right🥤
Multiple cursors plugin for vim/neovim
A minimal GPU design in Verilog to learn how GPUs work from the ground up
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
Instruction Set Generator initially contributed by Futurewei
📸 Snapshot plugin with rich features that can make pretty code snapshots for Neovim
Make your nvim window separators colorful
Verilog AXI components for FPGA implementation
A lightweight coding agent for open models like Deepseek, Kimi, and Qwen
Fast and accurate DRAM power and energy estimation tool
Common SystemVerilog components
✨ Clarify and beautify your comments and plain text files using boxes and lines.
Repository to host and maintain SCALE-Sim code
🚀✨ Help beginners to contribute to open source projects
Generic Register Interface (contains various adapters)
SystemVerilog modules and classes commonly used for verification