Skip to content
View bhza's full-sized avatar
:dependabot:
Working f anywhere n anyplace automating everything around as much as possible.
:dependabot:
Working f anywhere n anyplace automating everything around as much as possible.

Block or report bhza

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

3 stars written in Verilog
Clear filter

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,932 892 Updated Jun 27, 2024

FPGA, ASIC Tasarımı, RF ve Gömülü Sistemler üzerine teknik notlar, RTL denemeleri ve yüksek hızlı dijital tasarım prensiplerini içeren kişisel mühendislik defteri. ⚡🛠️

Verilog 9 Updated Dec 11, 2025

Course project of Computer Architecture, designed by single-cycle datapath. The verilog code could be completely compiled by Quartus II.

Verilog 1 Updated Feb 14, 2021