Minimal examples of DPDK

microbenchmark for generating RDMA RC traffic

🔥 Real-time NVIDIA GPU dashboard

Sample code from thegeekinthecorner.com

HPC research and demonstrations

Braincraft challenge — 1000 neurons, 100 seconds, 10 runs, 2 choices, no reward

A collection of fluid simulations

Xv6 for RISC-V with Networking

Doom classic port to lightweight RISC‑V

NVIDIA Linux open GPU with P2P support

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

The tool is designed to provide high DPDK performances to burst any pcap dump on a single or multiple NIC port(s)

A collection of awesome researchers and papers about disaggregated memory.

10-stage out-of-order RV64IMAFDC CPU

A highly-configurable RISC-V Core

VNx: Vitis Network Examples

Verilog PCI express components

Tutorials and useful scripts for using RapidStream.

Tutorial for CPU-FPGA communication using Xilinx FPGAs on Alibaba Cloud with PCIe and XRT.

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

All About HDL

C++ interfaces for RDMA access

Demo of a pulse-per-second timer on Tang Nano board FPGAs

PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers

CoreSight trace stream decoder developed openly

Implementing a Virtio-compliant interface on the FPGA

Scorpi - A Modern Hypervisor (for macOS)

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt