Release Notes

Full Changelog: v2.0...v2.1

General bug-fixes
- Fixed illegal detection of vector widening, extension, load, store and register gather instructions
- Fixed dcache coalescing setting
- Fixed WFI instruction wrongly resuming the core with interrupts disabled
- Fixed unconnected HPM counter on simulation
- Fixed mtval CSR value on exception & mepc CSR lower bits
Improved Konata and commit log dumps
Updated dcache to newer version
Unified integer, floating point and vector register files under the same system verilog module

NOTE This release is just a mirror of the one in the sargantana repository, from now on, releases will be mirrored on both repositories

Upgraded RISC-V Vector Extension (RVV) support
- Moved from a small subset of instructions from version 0.7 to supporting most of the 1.0 specification.
- Missing RVV 1.0 features are support for LMUL>1 (vector lenght multiplier, refers to the number of vector registers per vector register group) and vector floating-point instructions.
- Added register renaming for vector configuration-setting instructions (vsetvli/vsetivli/vsetvl) resulting in improved performance.
Added support for RISC-V Debug Specification.
- Support for the Debug Module (DM) non-ISA Extension.
- Support for Sdext ISA extension.
Added support for RISC-V Sscofpmf ISA extension to allow reading Sargantana performance counters in Linux via perf.
Added support for RISC-V B ISA extension (Standard Extension for Bit Manipulation Instructions) which includes the Zba, Zbb and Zbs extensions.
Sargantana + HPDCache has been integrated into the OpenPiton framework with 3 levels of caches. This allows us to support booting Linux with a multi-core configuration.
Enhanced RTL simulation environment by adding support for the Verilator save and restore feature. This enables the creation of checkpoints during the simulation that can be later resumed.
General bug-fixes and code style improvements.

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