Stars
Blackwire SpinalHDL components implementing WireGuard primitives
Axion-HDL: Automated AXI Register Space Generation Tool
An open-source HDL register code generator fast enough to run in real time.
Generates simple AXI4-lite IP for use in Vivado from register specifications
IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.
An open source high level synthesis (HLS) tool built on top of LLVM
Open-Source HLS Examples for Microchip FPGAs
A simple vector add tutorial for Xilinx Vivado, Xilinx Vivado HLS, and Xilinx SDK on zedboard
Open source, local, and self-hosted Amazon Echo/Google Home competitive Voice Assistant alternative
AudioWagon will play audio files from an attached USB flash drive in cars equipped with Android Automotive OS
A real-time, offline voice assistant for Linux and Raspberry Pi. Uses local LLMs (via Ollama), speech-to-text (Vosk), and text-to-speech (Piper) for fast, wake-free voice interaction. No cloud. No …
Open-Source Battery Monitoring & Modeling Resources
Run a 1-billion parameter LLM on a $10 board with 256MB RAM
Open source FPGA-based NIC and platform for in-network compute
A lightweight, object-oriented finite state machine implementation in Python with many extensions
System support for long-running programs on RFID-scale devices
GateMate's PHY Interface for PCI Express (PIPE)
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Arxml Editor, using Eclipse XML Editor