Solve naming conflict with Yosys #3673
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Yosys and other synthesis tools already have internal ALU blocks which collide with a module named ALU
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Contributor
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@leviathanch you need to amend that commit to include a email that is associated with your Github account, such that the EasyCLA can work. |
Contributor
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I think this change is pragmatic, but tools like Yosys really should handle collisions with user-defined modules in ways that don't require you to rename your module. |
Contributor
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The real bug is the lack of packages/namespaces in Verilog though... |
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Yosys and other synthesis tools already have internal ALU blocks which collide with a module named ALU