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5 results for source starred repositories written in Verilog
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The USRP™ Hardware Driver Repository

Verilog 1,197 738 Updated Jan 20, 2026

SDRAM controller with multiple wishbone slave ports

Verilog 29 12 Updated Oct 26, 2018

SDRAM controller optimized to a memory bandwidth of 316MB/s

Verilog 29 5 Updated Aug 16, 2021

Trojan Hardware implemented in the OpenCores Amber ARM Core

Verilog 7 2 Updated Mar 17, 2014

This project explores the detection of hardware trojans using delay-based methods on FPGAs. The study builds upon a previous project and addresses challenges while exploring various scenarios. The …

Verilog 1 Updated Jul 3, 2023