Starred repositories
The Vulkan API Specification and related tools
A tool and a library for bi-directional translation between SPIR-V and LLVM IR
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the…
256-bit vector processor based on the RISC-V vector (V) extension
A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Bluetooth Low Energy (BLE) packet sniffer and transmitter for both standard and non standard (raw bit) based on Software Defined Radio (SDR).
The code & assets for Godot/C# tutorials I published in video/text format on YouTube and Medium (🇬🇧 + 🇫🇷).
A visual simulator for teaching computer architecture using the RISC-V instruction set
This repository contains openlane configuration and source files for tutorials that I created
Standard Cell Library based Memory Compiler using FF/Latch cells
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
A digital logic designer and circuit simulator.
Single-cycle MIPS processor in Verilog HDL.
This github repo is to document the 5day "RTL Design and Synthesis using Verilog and Sky130 library" which was conducted by VLSI System Design Corp.
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.