Performance: BlockTile 256x128 optimizations enable 1500+ TF FP8 #81
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…performance on the H800-SXM platform
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soundOfDestiny
approved these changes
Apr 9, 2025
zheanxu
approved these changes
Apr 9, 2025
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By resuing the Accumulator registers of Tensor Cores to implement a 256x128 BlockTile structure, this approach significantly increases data reuse, reduces the demand for L2 Cache and HBM memory accesses, and enhances the SM's computational frequency, ultimately achieving FP8 performance exceeding 1,500+ TFLOPS.
Test on “H800”-SXM && CUDA 12.8.1