Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/

mdbook for Modern CPP

Linux on LiteX-VexRiscv

Build your hardware, easily!

RISC-V Open Source Supervisor Binary Interface

Python module containing verilog files for VexRiscv SMP CPU (for use with LiteX).

VexRiscv CPU implementation with CLIC support

Python module containing verilog files for vexriscv cpu with CLIC (for use with LiteX).

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

Python module containing system_verilog files for ibex cpu (for use with LiteX).

Python module containing sources files for minerva cpu (for use with LiteX).

Home of the open-source EDA course.

Like VexRiscv, but, Harder, Better, Faster, Stronger

Blog Template for Mkdocs

A demo system for Ibex including debug support and some peripherals

German Book