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A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。
Changed the pcileech-fpga project to support custom register access functionality and a DNA bidirectional communication encryption verification system based on this functionality.
Fullstack app framework for web, desktop, and mobile.
My first implementation of a cheat trainer using Direct Memory Access (DMA) for AssaultCube. Created as a learning exercise in external memory manipulation and reverse engineering
Shows an example of how to implement VT-d/AMD-Vi on Windows
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Asterinas is a secure, fast, and general-purpose OS kernel, written in Rust and providing Linux-compatible ABI.
A DDR3 memory controller in Verilog for various FPGAs
Tools for accessing a floppy drive at the raw flux level
This guide leverages QEMU on unix to capture and analyze PCIE devices
Universal utility for programming FPGA
Basic USB 1.1 Host Controller for small FPGAs
Notes and utilities for reverse engineering Agilent PCIe Protocol Analyzers and their host software.
Notes and utilities for reverse engineering USB-to-PCIe/NVMe controllers.
PCILeech module to exploit Windows 10 from UEFI when OS DMA protection is enabled
memflow connector backend to interface with pcileech devices
real time face swap and one-click video deepfake with only a single image
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…
A TTS model capable of generating ultra-realistic dialogue in one pass.
Expanding PCILeech support for affordable LiteFury FPGA hardware (Artix-7) to facilitate malware analysis. Repository contains digital designs, Verilog scripts, XDC constraints, and drivers for Lit…
SMM UEFI module and client for UMD privilege escalation
System Management Mode (SMM) game cheating framework