Linux kernel source tree

Visual Studio Code

uBlock Origin - An efficient blocker for Chromium and Firefox. Fast and lean.

Git Source Code Mirror - This is a publish-only repository but pull requests can be turned into patches to the mailing list via GitGitGadget (https://gitgitgadget.github.io/). Please follow Documen…

ShellCheck, a static analysis tool for shell scripts

Concise, consistent, and legible badges in SVG and raster format

A brief computer graphics / rendering course

cloc counts blank lines, comment lines, and physical lines of source code in many programming languages.

Run compilers interactively from your web browser and interact with the assembly

Simple DirectMedia Layer

Chrome extension to return youtube dislikes

Useful CMake Examples

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Simple animated GIF screen recorder with an easy to use interface

Semantic Versioning Specification

If you build software, keep a changelog.

RISC-V Instruction Set Manual

Verilator open-source SystemVerilog simulator and lint system

🌊 Digital timing diagram rendering engine

VHDL 2008/93/87 simulator

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Use ripgrep to find TODO tags and display the results in a tree view

32-bit Superscalar RISC-V CPU

🚀 Easy way to know how many visitors are viewing your Github, Website, Notion. 🎉

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

Read-only mirror of https://gitlab.gnome.org/GNOME/gnome-shell

VeeR EH1 core