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Starred repositories

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Linux kernel source tree

C 216,219 60,290 Updated Feb 4, 2026

Visual Studio Code

TypeScript 181,339 37,734 Updated Feb 4, 2026

uBlock Origin - An efficient blocker for Chromium and Firefox. Fast and lean.

JavaScript 61,326 3,928 Updated Feb 3, 2026

Git Source Code Mirror - This is a publish-only repository but pull requests can be turned into patches to the mailing list via GitGitGadget (https://gitgitgadget.github.io/). Please follow Documen…

C 58,900 27,429 Updated Feb 3, 2026

ShellCheck, a static analysis tool for shell scripts

Haskell 38,933 1,897 Updated Feb 1, 2026

Concise, consistent, and legible badges in SVG and raster format

JavaScript 26,027 5,581 Updated Feb 3, 2026

A brief computer graphics / rendering course

C++ 23,188 2,210 Updated Nov 21, 2025

cloc counts blank lines, comment lines, and physical lines of source code in many programming languages.

Perl 22,498 1,092 Updated Jan 26, 2026

Run compilers interactively from your web browser and interact with the assembly

TypeScript 18,519 1,988 Updated Feb 4, 2026

Simple DirectMedia Layer

C 14,791 2,594 Updated Feb 4, 2026

Chrome extension to return youtube dislikes

JavaScript 13,457 602 Updated Dec 12, 2025

Useful CMake Examples

CMake 13,066 2,549 Updated Feb 28, 2024

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SystemVerilog 11,236 950 Updated Aug 18, 2024

Simple animated GIF screen recorder with an easy to use interface

Vala 10,567 338 Updated Sep 24, 2025

Semantic Versioning Specification

7,668 752 Updated Nov 5, 2025

If you build software, keep a changelog.

Haml 6,489 3,581 Updated Jan 7, 2026

RISC-V Instruction Set Manual

TeX 4,480 791 Updated Feb 3, 2026

🌊 Digital timing diagram rendering engine

JavaScript 3,337 399 Updated Jul 10, 2025

Verilator open-source SystemVerilog simulator and lint system

SystemVerilog 3,334 749 Updated Feb 4, 2026

VHDL 2008/93/87 simulator

VHDL 2,742 402 Updated Feb 3, 2026

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,481 320 Updated Jan 7, 2026

πŸ–₯️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VHDL 1,975 304 Updated Feb 3, 2026

Use ripgrep to find TODO tags and display the results in a tree view

JavaScript 1,713 162 Updated Apr 13, 2024

32-bit Superscalar RISC-V CPU

Verilog 1,175 200 Updated Sep 18, 2021

πŸš€ Easy way to know how many visitors are viewing your Github, Website, Notion. πŸŽ‰

Go 1,141 104 Updated Aug 18, 2024

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog 960 328 Updated Nov 15, 2024

Read-only mirror of https://gitlab.gnome.org/GNOME/gnome-shell

JavaScript 922 205 Updated Feb 3, 2026

VeeR EH1 core

SystemVerilog 921 235 Updated May 29, 2023

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

C 900 152 Updated Feb 2, 2026

Integrates ShellCheck into VS Code, a linter for Shell scripts.

TypeScript 898 46 Updated Feb 3, 2026
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