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Starred repositories

5 stars written in Verilog
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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,529 322 Updated Jan 7, 2026

32-bit Superscalar RISC-V CPU

Verilog 1,223 202 Updated Sep 18, 2021

RISC-V Formal Verification Framework

Verilog 629 103 Updated Apr 6, 2022

RISC-V microcontroller IP core for embedded, FPGA and ASIC applications

Verilog 194 27 Updated Apr 10, 2026

Dual-issue RV64IM processor for fun & learning

Verilog 64 9 Updated Jul 4, 2023