This project demonstrates a scalable format for Verilog including build scripts, design verification, and synthesis.

RVX HAL - Hardware Abstraction Layer

RISC-V Scratchpad

SystemVerilog/Verilog support for vscode using Ctags

Dual-issue RV64IM processor for fun & learning

RISC-V Formal Verification Framework

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Web-based RISC-V superscalar simulator

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

32-bit Superscalar RISC-V CPU

Guide for hacking your reMarkable tablet

RISC-V Nox core

RISC-V Processor written in Amaranth HDL

RISC-V microcontroller IP core for embedded, FPGA and ASIC applications

VeeR EH1 core

Hardened RISC-V core

uBlock Origin - An efficient blocker for Chromium and Firefox. Fast and lean.

A brief computer graphics / rendering course

Use ripgrep to find TODO tags and display the results in a tree view

HDL support for VS Code

Simple DirectMedia Layer

Useful CMake Examples

🖥️ Show current CPU usage, memory usage and net speed on panel

A GNOME Shell extenesion to hide Universal Access icon from the status bar

Mute/Unmute Gnome extension

A live viewer for reMarkable written in PyQt5

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations