Skip to content
View dsfb's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report dsfb

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

4 stars written in Verilog
Clear filter

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,838 885 Updated Jun 27, 2024

Open source implementation of a x86 processor

Verilog 332 74 Updated Apr 15, 2018
Verilog 214 43 Updated Jun 25, 2025

Original RISC-V 1.0 implementation. Not supported.

Verilog 42 14 Updated Oct 4, 2018