explorations of bazel, support for a serie of articles and to experiment stuff on bazel.

A core language for rule-based hardware design 🦑

Yosys Open SYnthesis Suite

Random instruction generator for RISC-V processor verification

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

A flexible linter with rules defined by regular expression

SystemVerilog language server client for Visual Studio Code

A sample project of svlint plugin

SystemVerilog linter

SystemVerilog parser library fully compliant with IEEE 1800-2017

SystemVerilog to Verilog conversion

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity

Guarded Atomic Actions for HardCaml

SonicBOOM: The Berkeley Out-of-Order Machine

The Shang high-level synthesis framework

Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs

An open-source static random access memory (SRAM) compiler.

Flexible Intermediate Representation for RTL

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

(a maintenance fork of the) Open source library for SPI/I2C control via FTDI chips

Hammer: Highly Agile Masks Made Effortlessly from RTL

Java Constraint Programming solver