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Commits on May 30, 2019

• microblaze: add SPI clock constraint

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• zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS

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• axi_fmcadc5_sync: define spi clock constraint

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• adrv9361z7035:ccfmc_constr.xdc: constrain all input clocks

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• fmcomms5: constrain ref clock

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• vc707: define 125 MHz SGMII clock

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Commits on May 24, 2019

• scripts/adi_project.tcl: make search for undefined clocks more robust

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• axi_dmac: version bump for minor patches

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• axi_dmac: clear measured transfer length when core disabled

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• axi_dmac: fix transfer length reporting cyclic mode

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• axi_dmac: patch xfer_request

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• axi_dmac: patch for partial transfers support

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• axi_dmac: patch for partial 2D transfer support

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• scripts/adi_project:adi_project_alt: add parameters to top level

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• jesd204:tpl: add missing dependencies for Intel

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Commits on May 16, 2019

• scripts:adi_project.tcl: add check for missing clock definitions

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• ad9208_dual_ebz: Initial version

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• jesd204_rx: add parameter for input pipeline stages

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• daq3:qsys: use bundled AXIS interface

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• daq2:qsys: use bundled AXIS interface

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• aradio:qsys: use bundled AXIS interface

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• adrv9371:qsys: use bundled AXIS interface

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• adrv9009:qsys: use bundled AXIS interface

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• util_upack2: bundle AXIS signals into bus for Intel

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• util_adcfifo/util_dacfifo: bundle AXIS signals into bus for Intel

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• avl_dacfifo: bundle AXIS signals into bus

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• axi_dmac: bundle AXI Stream signals into bus for Intel

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• Revert "axi_dmac: add tlast to the axis interface for Intel"

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• jesd204/scripts: fix indentation

  

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• jesd204/scripts: TPL add support for M=1

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Commits on May 9, 2019

• util_adxcvr: Expose GTY4 parameters required for 15Gbps link

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Commits on Apr 25, 2019

• axi_dmac: infer interrupt line for Xilinx projects

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Commits on Apr 23, 2019

• scripts: patch incremental compile

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Commits on Apr 22, 2019

• scripts: Support for incremental compilation

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• axi_mc_controller:axi_mc_current_monitor: define generated clocks in IP constraints file for better OOC integration

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