Test and calibration for the Wedgetail project on TinyTapeout IHP26a

Stores your data in ICMP ping packets

Self-contained RTL to GDS flow for simple chip designs

Some BASIC games I wrote for the TI-84 (Snake, Space Invaders, racing, Pong)

Open Source Silicon Development Testing Unit using JTAG

RISC-V Debug Support for our PULP RISC-V Cores

GL0AM GPU Accelerated Gate Level Logic Simulator

Ariane is a 6-stage RISC-V CPU

A QSPI Pmod board designed in KiCad containing one Flash and two SPRAMs

Tiny Tapeout GDS Online Viewer

ASIC implementation flow infrastructure, successor to OpenLane

Converts GDSII files to STL files.

A Risc-V SoC for Tiny Tapeout

TinyQV - Crowdsourced Risc-V SoC

The single instruction language - Flip a bit, then Jump

TinyTapeout demo pcb's RP2040 functionality

Home of the open-source EDA course.

A bit-serial CPU written in VHDL, with a simulator written in C.

The next generation of OpenLane, rewritten from scratch with a modular architecture

GPU-based logic synthesis tool

Convert a Python dictionary to an indented Liberty file