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@ZipCPU
Dan Gisselquist ZipCPU

Gisselquist Technology, LLC

@amiq-consulting
AMIQ Consulting amiq-consulting
AMIQ Consulting was founded in 2003 to provide design and pre-silicon verification services.

AMIQ Consulting Bucharest, Romania

@rggen
RgGen rggen
Code generation tool for control and status registers
@wavedrom
WaveDrom wavedrom
Digital timing diagram (waveform) rendering engine that uses JavaScript to convert JSON description into SVG.

Earth

@pyuvm
pyuvm pyuvm
The UVM IEEE 1800.2 Standard implemented in Python
@antmicro
Antmicro antmicro
Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.
@ossu
Open Source Society University ossu
Empowering learners to master college curricula through free resources. Choose a major and start today!
@SystemRDL
SystemRDL SystemRDL
Free & open-source SystemRDL tools
@mara
Mara mara
Lightweight data warehousing in Python

Berlin, Germany

@ekiwi
Kevin Laeufer ekiwi
Modern Hardware Construction Languages and Automated Testing

Cornell University Ithaca, NY

@fvutils
Functional Verification Utilities fvutils
Modern, Python-centric tools for functional verification engineers and developers
@raysalemi
Ray Salemi raysalemi
I teach physics and engineering at Natick High School. In the past, I was a computer engineer, and I wrote the initial version of pyuvm and The UVM Primer.

Natick High School Boston, MA

@yuuhe4fun
RyanHe yuuhe4fun
Yu HE currently works at the School of Integrated Circuit Science and Engineering, Beihang University, pursuing his PhD degree in AP. Guang YANG’s group.

Beihang University Beijing

@jserv
Jim Huang jserv

@BiiLabs Taipei City, Taiwan

@AdDraw
Adam Drawc AdDraw

Intel Warsaw, PL

@chipsalliance
CHIPS Alliance chipsalliance
Common Hardware for Interfaces, Processors and Systems
@enjoy-digital
enjoy-digital

EnjoyDigital France

@gr33nka
Mikhail Popov gr33nka
Hardware Research Engineer

BSC-CNS

@hanysalah
Hany Salah hanysalah
CPU Verification Engineer

Imagination Technologies United Kingdom

@ShashankVM
Shashank V M ShashankVM
Electronics engineer

@graphcore Karnataka, India

@raulbehl
raulbehl
Computer Architecture Enthusiast, Verilog & Assembly level programmer
@hellgate202
Leonid Ivanov hellgate202
FPGA engineer. Specialized in Ethernet and video processing

Russian Federation, Saint-Petersburg

@vha3
V. Hunter Adams vha3
Lecturer of aerospace engineering and electrical engineering at Cornell University. Likes space, electronics, and everything else.
@smirnovich
Daniil smirnovich
VHDL addicted, Python enjoyer

Scantinel Photonics Ulm, Germany

@black-parrot
Black Parrot black-parrot
The Black Parrot RISC-V Linux-Capable Multicore
@IObundle
IObundle, Lda IObundle
Custom Computing Machines
@jjts
Jose T. de Sousa jjts
RISC-V enthusiast Embedded hardware and software IP cores

IObundle, Lda Lisbon

@whitequark
Catherine whitequark
the catgirl knows where it is at all times

@SCISemi UK

@tomverbeure
Tom Verbeure tomverbeure
24/7 electronics (and some biking)

Sunnyvale, CA

@ValentiWorkLearning
Valentyn Korniienko ValentiWorkLearning
C++ Embedded/Software developer

Luxoft Ukraine, Kharkiv

@zhelnio
Stanislav Zhelnio zhelnio
RTL Design Engineer

Russia, Moscow

@Dmitriy0111
Vlasov Dmitriy Dmitriy0111
Development and verification of projects for FPGA (Verilog, SystemVerilog)

Russia, Novosibirsk

@TishukBogdana
posedge clk TishukBogdana
Hardware Engineer | DSP enthusiast | EE (Negative Group Delay circuits ) Researcher

Beijing

@drom
Aliaksei Chapyzhenka drom
always @ posedge

@sifive Terra ⴲ

@kelu124
K. Ghosh kelu124
Purpose-driven digit, also doing hardware, ultrasound imaging, n00b in Python, and experimenting in LLMs and others =

Paris

@dotcypress
Vitaly Domnikov dotcypress
🇺🇦🇺🇸 OSS/OSH Advocate, console.log Expert.

ДСК

@bunnie
bunnie bunnie
Good at following directions. Bad at obeying rules.

Singapore

@NickolayTernovoy
Nickolay NickolayTernovoy
RTL design engineer; telegram: https://t.me/cpu_design

Semidynamics

@alexforencich
Alex Forencich alexforencich

UC San Diego La Jolla, CA