MIT 6.828 操作系统工程 2018 fall labs & notes

mit 6.828 2018，JOS实现

Documentation for XiangShan

Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.

Icarus Verilog

Working draft of the proposed RISC-V V vector extension

Keystone Enclave (QEMU + HiFive Unleashed)

Code from various chapters in OSTEP (http://www.ostep.org)

A cross-platform, linkable library implementation of Git that you can use in your application.

UNIX-like reverse engineering framework and command-line toolset

Use D3 to visualize simple git branching operations.

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Ultralytics YOLO 🚀

YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite

This is my code for labs and projects for 6.175 (Constructive Computer Architecture)

【编程随想】收藏的电子书清单（多个学科，含下载链接）

This is a repository containing solutions to the problem statements given in HDL Bits website.

掌握、理解Docker容器技术，从真实案例中学习最佳实践技巧！| Learn and understand Docker&Container technologies, with real DevOps practice!

Bluespec Compiler (BSC)

MIT6.175 & MIT6.375 Study Notes

Connectal is a framework for software-driven hardware development.

关于RISC-V你所需要知道的一切

Tiny, fast(ish), self-contained, fully loaded printf, sprinf etc. implementation; particularly useful in embedded systems.

Rust symbol demangling

Demangle Rust symbols