Stars
7
stars
written in VHDL
Clear filter
Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
A comparison of 1st and 2nd order sigma delta DAC for FPGA
A SystemVerilog implementation of MIPS32 CPU and RIP router