3D-ICE Official github repository

⚡ Build your chatbot within minutes on your favorite device; offer SOTA compression techniques for LLMs; run LLMs efficiently on Intel Platforms⚡

Code for the paper "Exploration by Random Network Distillation"

Random Network Distillation pytorch

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)

Ariane is a 6-stage RISC-V CPU

Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.

[DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs

Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)

Source Code for training and evaluating BranchNet models for branch prediction

Mamba SSM architecture

Open Circuit Benchmark OCB and source code for CktGNN (https://openreview.net/forum?id=NE2911Kq1sp).

Instruction Set Generator initially contributed by Futurewei

GPU-enabled Hardware Fuzzer using Genetic Algorithm

Everything you need about Active Learning (AL).

Benchmark present methods for efficient reinforcement learning. Methods include Reptile, MAML, Residual Policy, etc. RL algorithms include DDPG, PPO.

The Places365-CNNs for Scene Classification

Implementations of basic RL algorithms with minimal lines of codes! (pytorch based)

Fork of upstream onnxruntime focused on supporting risc-v accelerators

Spike, a RISC-V ISA Simulator

Freedom U Software Development Kit (FUSDK)

Run Linux on RISC-V Spike Simulator

Model-based Policy Gradients

DEPRECATED - please visit https://github.com/vwxyzjn/ppo-implementation-details

Neural network graphs and training metrics for PyTorch, Tensorflow, and Keras.

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro