RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

Verilog SDRAM memory controller

Mega Drive/Genesis core written in Verilog

Example designs showing different ways to use F4PGA toolchains.

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

This is an attempt to make clean Verilog sources for each chip on the Amiga.

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

Sega Genesis for MiSTer

FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

CPLD Replacement for A2000 Buster

Spitfire 500, A low-end 14 MHz Accelerator with IDE and 4/8 MB fast RAM for the Amiga 500.

Reverse-engineering of SEGA chips

Verilog code to replace the Commodore SDMAC found in the A3000

Terriblefire TF1230

David's ST Booster

8MB autoconfig fast memory for the Amiga 2000

Implementation of 8250 Complex Interface Adapter (CIA) in Verilog

Verilog models for the GAL22V10 and select PAL devices.

Firmware for the Spitfire 2000 Amiga Accelerator

Mirror of tf530 repository

m68k based System on Chip

Finally, a CPU that isn't mind-numbingly complex. Batteries sold separately.

Amiga 2000 Zorro II Fast RAM Expansion

tf530