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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
verilator / uvm
Forked from chipsalliance/uvm-verilatorUniversal Verification Methodology (UVM) base libraries, with edits for Verilator