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Sapere aude.
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Sapere aude.
17 followers · 34 following

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Achievement: Pair Extraordinairex2Achievement: StarstruckAchievement: YOLOAchievement: Pull Sharkx2Achievement: Arctic Code Vault Contributor

Achievements

Achievement: Pair Extraordinairex2Achievement: StarstruckAchievement: YOLOAchievement: Pull Sharkx2Achievement: Arctic Code Vault Contributor

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@cad-polito-it

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Lists (2)

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6 results for source starred repositories written in Verilog
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YosysHQ / picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,757 871 Updated Jun 27, 2024

nvdla / hw

RTL, Cmodel, and testbench for NVDLA

Verilog 1,961 622 Updated Mar 2, 2022

pulp-platform / cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Verilog 295 83 Updated Oct 31, 2025

freecores / can

CAN Protocol Controller

Verilog 39 17 Updated Jul 17, 2014

freecores / xilinx_virtex_fp_library

Xilinx Virtex FLoating Point

Verilog 7 5 Updated Jul 17, 2014

freecores / fpu

Floating Point Unit

Verilog 7 1 Updated Jul 17, 2014