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Mojo-V: A RISC-V instruction set extension for privacy-oriented programming. Mojo-V allows programmers to write software that computes on data that no software or person can see, except the data ow…
riscv / riscv-worlds
Forked from riscv/riscv-isa-manualRISC-V Worlds provides isolation in a hardware platform by constraining access to system physical addresses.
Embedded Test (ET) -- The Super-Simple Embedded Test
统计 Git 项目的 commit 时间分布，进而推导出项目的编码工作强度。 Analyzes the commit time distribution of Git projects to infer coding work intensity.
Tutorial on how to run OP-TEE on the Raspberry Pi 5.
《Performance Analysis and Tuning on Modern CPUS - 2ed》的非专业个人翻译
cloc counts blank lines, comment lines, and physical lines of source code in many programming languages.
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Reference implementation of RPMI specification as a library.
Linux running inside a PDF file via a RISC-V emulator
The book "Performance Analysis and Tuning on Modern CPU"
The RISC-V External Debug Security Specification
Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate …
GNU toolchain for RISC-V, including GCC
This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM …
This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator developm…
Modular visual interface for GDB in Python
Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware.