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Pull requests: gem5/gem5

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Pull requests list

arch-arm, stdlib: Rework the PTW to support a configurable number of outstanding TW arch-arm The ARM ISA stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2650 opened Oct 8, 2025 by giactra Loading…
stdlib: Support generation of multiple directories in CHI stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2648 opened Oct 8, 2025 by giactra Loading…
3
stdlib: Define a new get_mem_ranges method stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2647 opened Oct 7, 2025 by giactra Loading…
4
mem-cache: Remove unused header in prefetch mem General Memory Systems (e.g., XBar, Packet)
#2644 opened Oct 7, 2025 by powerjg Loading…
dev-amdgpu,stdlib: Allow for multiple GPUs in stdlib gpu gem5's GPU Simulation infrastructure stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2633 opened Oct 4, 2025 by abmerop Loading…
22
arch-arm: Add support for LRCPC instructions arch-arm The ARM ISA
#2632 opened Oct 4, 2025 by pranith Loading…
10
mem-cache: Add unit test for MRU RP mem General Memory Systems (e.g., XBar, Packet)
#2630 opened Oct 2, 2025 by odanrc Loading…
arch-riscv: fix vm* for VLEN/EEW < 8 and LMUL > 1 arch-riscv The RISC-V ISA
#2626 opened Oct 2, 2025 by Joao-Pedro-Cabral Loading…
1
arch-arm: Decouple insts from generated decoder arch-arm The ARM ISA
#2623 opened Oct 1, 2025 by powerjg Loading…
1
arch-arm,cpu-o3,base: Fix Ubsan warning arch-arm The ARM ISA base Regards gem5's base code. Found in "src/base" cpu-o3 gem5's Out-Of-Order CPU
#2616 opened Sep 30, 2025 by rogerchang23424 Loading…
3
Fdp-library arch-x86 The X86 ISA cpu General gem5 CPU code (e.g., `BaseCPU`) cpu-o3 gem5's Out-Of-Order CPU mem General Memory Systems (e.g., XBar, Packet) stdlib The gem5 standard library. Code typically found under "src/pythongem5" tests gem5's Testing Infrastructure
#2595 opened Sep 17, 2025 by dhschall • Draft
base: reduce write syscalls in stats output base Regards gem5's base code. Found in "src/base"
#2578 opened Sep 7, 2025 by heshpdx Loading…
dev: add PCI to PCI bridge dev General gem5 development code. Found in "src/dev"
#2561 opened Sep 1, 2025 by clemdiep Loading…
9
Install protobuf from source instead of APT misc Anything outside of the current labeling categories
#2557 opened Aug 28, 2025 by Sir-NoChill Loading…
1
mem, tests: Add SimObject unit tests for the TreePLRU replacement policy mem General Memory Systems (e.g., XBar, Packet) tests gem5's Testing Infrastructure
#2548 opened Aug 21, 2025 by erin-le Loading…
38
sim: Allow int64_t source to bind integral sink sim General gem5 Simulation Components
#2528 opened Aug 13, 2025 by dl8sd11 Loading…
3
cpu-o3: Bundle some Fetch/IEW/Commit stats into a vector cpu-o3 gem5's Out-Of-Order CPU
#2518 opened Aug 7, 2025 by dhschall Loading…
3
sim, cpu: DRAFT - try to make Simulator.schedule_max_insts use hypercalls cpu General gem5 CPU code (e.g., `BaseCPU`) sim General gem5 Simulation Components
#2514 opened Aug 6, 2025 by erin-le • Draft
2
stdlib: Add estimated instructions to WorkloadResource stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2471 opened Jul 24, 2025 by erin-le Loading…
3
cpu,sim,switch: Fix assertion failure in switchable CPUs due to doClone cpu General gem5 CPU code (e.g., `BaseCPU`) sim General gem5 Simulation Components
#2456 opened Jul 17, 2025 by alisemi Loading…
1
8
WIP: MI300X Multi chiplet sim related file changes gpu gem5's GPU Simulation infrastructure gpu-compute gem5's GPU Compute Code stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2434 opened Jul 9, 2025 by ronpower7 • Draft
28
Merging gem5-SALAM code
#2429 opened Jul 8, 2025 by akanksha-sc • Draft
31
dev: Make DmaPort can be inherited dev General gem5 development code. Found in "src/dev"
#2424 opened Jul 4, 2025 by wmin0 Loading…
6
arch: Update ISA parser to be moveable arch General gem5 architecture-specific components arch-x86 The X86 ISA
#2406 opened Jun 27, 2025 by powerjg Loading…
5
mem-ruby: Update slicc to use relative imports mem-ruby Ruby caches, structures, and protocols
#2405 opened Jun 27, 2025 by powerjg Loading…
3
ProTip! What’s not been updated in a month: updated:<2025-09-08.