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classic cache Prefetcher: Why is there no simple next-line prefetcher

mem-cacheClassic caches and coherenceClassic caches and coherence

Status: Open.

#2838 In gem5/gem5;

· Ywinh opened on Dec 16, 2025

Stat filename is a python list when using multisim

bug

stdlibThe gem5 standard library. Code typically found under "src/pythongem5"The gem5 standard library. Code typically found under "src/pythongem5"

Status: Open.

#2835 In gem5/gem5;

· powerjg opened on Dec 15, 2025

·  

gem5 V25.1 PR checklist

script <code>util/decode_packet_trace.py</code> has not been maintained for a long time

utilUtilities for gem5. Typically found in "util"Utilities for gem5. Typically found in "util"

Status: Open.

#2831 In gem5/gem5;

· HUJIYONG opened on Dec 12, 2025

MSHR model

mem-cacheClassic caches and coherenceClassic caches and coherence

Status: Open.

#2825 In gem5/gem5;

· yangguoming opened on Dec 10, 2025

x86 kvm support for linux kernel greater than 6.8.0

arch-x86The X86 ISAThe X86 ISA

cpu-kvmgem5's KVM CPUgem5's KVM CPU

Status: Open.

#2821 In gem5/gem5;

· jerryidk opened on Dec 9, 2025

RubyCache O3 CPU FIFO ordering violation

cpu-o3gem5's Out-Of-Order CPUgem5's Out-Of-Order CPU

mem-rubyRuby caches, structures, and protocolsRuby caches, structures, and protocols

Status: Open.

#2816 In gem5/gem5;

· AmoghBhagwat opened on Dec 7, 2025

APU model SE simulation: changes of frequency lead to changes of IPC

bug

gpugem5's GPU Simulation infrastructuregem5's GPU Simulation infrastructure

sim-segem5's Syscall Emulation Modegem5's Syscall Emulation Mode

Status: Open.

#2810 In gem5/gem5;

· Qantals opened on Dec 5, 2025

cpu-o3: IPC performance degradation in decoupled front-end

bug

cpu-o3gem5's Out-Of-Order CPUgem5's Out-Of-Order CPU

Status: Open.

#2808 In gem5/gem5;

· ChoungJX opened on Dec 5, 2025

mem-garnet: adding chiplet support/templates

mem-garnetThe Garnet subcomponent of RubyThe Garnet subcomponent of Ruby

Status: Open.

#2801 In gem5/gem5;

· RyzenFromFire opened on Dec 3, 2025

mi300x: Segmentation fault by using m5 ops

bug

gpugem5's GPU Simulation infrastructuregem5's GPU Simulation infrastructure

Status: Open.

#2786 In gem5/gem5;

· henrick-bonda opened on Nov 28, 2025

Segmentation fault on RISC-V Vector instructions execution, with trace enabled

arch-riscvThe RISC-V ISAThe RISC-V ISA

bug

Status: Open.

#2758 In gem5/gem5;

· ipocentro87 opened on Nov 17, 2025

sim-se: wait4() does not return the correct status

bug

sim-segem5's Syscall Emulation Modegem5's Syscall Emulation Mode

Status: Open.

#2754 In gem5/gem5;

· nmosier opened on Nov 14, 2025