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misc: Weekly Repo Status: September 8 - September 15, 2026
miscAnything outside of the current labeling categoriesAnything outside of the current labeling categoriesStatus: Open.#3527 In gem5/gem5;- Status: Open.#3522 In gem5/gem5;
- Status: Open.#3511 In gem5/gem5;
- Status: Open.#3503 In gem5/gem5;
sim: Page deallocation uses wrong thread context
memGeneral Memory Systems (e.g., XBar, Packet)General Memory Systems (e.g., XBar, Packet)simGeneral gem5 Simulation ComponentsGeneral gem5 Simulation ComponentsStatus: Open.#3492 In gem5/gem5;mem-dram: DDR5 classes disagree with their cited datasheet in 5 parameters
memGeneral Memory Systems (e.g., XBar, Packet)General Memory Systems (e.g., XBar, Packet)mem-dramDRAM memory systems in gem5DRAM memory systems in gem5Status: Open.#3490 In gem5/gem5;[RFC] Move RISC-V vl/vtype out of PCState and stop modelling vset as a branch
arch-riscvThe RISC-V ISAThe RISC-V ISAsim-segem5's Syscall Emulation Modegem5's Syscall Emulation ModeStatus: Open.#3472 In gem5/gem5;RISC-V sysfutex asmtests fail with MinorCPU
arch-riscvThe RISC-V ISAThe RISC-V ISAcpu-minorgem5's Minor CPUgem5's Minor CPUtestsgem5's Testing Infrastructuregem5's Testing InfrastructureStatus: Open.#3465 In gem5/gem5;- Status: Open.#3454 In gem5/gem5;
stdlib,mem-ruby: Centralize network topology initialization
mem-rubyRuby caches, structures, and protocolsRuby caches, structures, and protocolsstdlibThe gem5 standard library. Code typically found under "src/pythongem5"The gem5 standard library. Code typically found under "src/pythongem5"Status: Open.#3450 In gem5/gem5;- Status: Open.#3449 In gem5/gem5;
arch-arm,tests: Resolve disabled 32-bit dual-core boot tests
arch-armThe ARM ISAThe ARM ISAtestsgem5's Testing Infrastructuregem5's Testing InfrastructureStatus: Open.#3448 In gem5/gem5;