Skip to content
View gs19980115's full-sized avatar

Block or report gs19980115

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
6 stars written in Verilog
Clear filter

Open source FPGA-based NIC and platform for in-network compute

Verilog 2,058 489 Updated Jul 5, 2024

IC design and development should be faster,simpler and more reliable

Verilog 1,972 591 Updated Dec 31, 2021

RTL, Cmodel, and testbench for NVDLA

Verilog 1,961 622 Updated Mar 2, 2022

Verilog library for ASIC and FPGA designers

Verilog 1,350 298 Updated May 8, 2024

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Verilog 231 49 Updated Feb 4, 2025

Designing Video Game Hardware in Verilog

Verilog 27 5 Updated Jan 5, 2020