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Paebbels / pyVHDLModel
Forked from VHDL/pyVHDLModelAn abstract language model of VHDL written in Python.
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Simple parser for extracting VHDL documentation
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
GitHub special files and paths, such as README, LICENSE, .github, docs, dependabot, workflows.
A powerful, innovative and intuitive EDA suite for everyone!
intergalaktik / ulx4m
Forked from emard/ulx3sPCB for ULX4M FPGA R&D board
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.