Skip to content
View hjgt's full-sized avatar

Block or report hjgt

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

wiki for FreeJoy project

318 44 Updated Feb 27, 2026

Menubar Tool to set Charge Limits and Prolong Battery Lifespan

Swift 9,019 330 Updated Apr 13, 2026

Bilibili 公开课目录

8,535 709 Updated Jun 22, 2020

This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.

Verilog 12 3 Updated Sep 6, 2023
JavaScript 124 13 Updated Jul 12, 2021

🔠Foreign language reading and translation assistant based on copy and translate.

TypeScript 17,581 1,942 Updated Feb 23, 2026

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Verilog 516 63 Updated Dec 10, 2022

Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm

Verilog 16 4 Updated May 28, 2015

Parameterized Booth Multiplier in Verilog 2001

Verilog 51 20 Updated Oct 30, 2022
Python 135 109 Updated Apr 19, 2018

Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder

Verilog 122 27 Updated Jan 26, 2013

Unsigned serial divider

Verilog 2 Updated Jul 17, 2014

a super-simple pipelined verilog divider. flexible to define stages

Verilog 60 15 Updated Jul 25, 2019

White Rabbit HSR gateware development. Forked from OHWR

VHDL 9 3 Updated Jun 23, 2016

8/4 bit divider

Verilog 1 1 Updated Jan 29, 2014

LimeSDR-Mini board FPGA project

Verilog 63 40 Updated Aug 27, 2022

跟着《自己动手写 CPU》书上写的 OpenMIPS CPU。

Verilog 1 Updated Apr 25, 2015

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,530 321 Updated Apr 14, 2026

FPGA-based Nintendo Entertainment System Emulator

Verilog 271 65 Updated Jan 16, 2024